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description designed for pulse-width modulated (pwm) current control of bipolar microstepping stepper motors, the a3972 is capable of continuous output currents to 1.5 a and operating voltages to 50 v. internal fixed off-time pwm current-control timing circuitry can be programmed via a serial interface to operate in slow, fast, and mixed current-decay modes. the desired load-current level is set via the serial port with two 6-bit linear dacs in conjunction with a reference voltage. the six bits of control allow maximum flexibility in torque control for a variety of step methods, from microstepping to full-step drive. load current is set in 1.56% increments of the maximum value. synchronous rectification circuitry allows the load current to flow through the low r ds(on) of the dmos output driver during the current decay. this feature will eliminate the need for external clamp diodes in most applications, saving cost and external component count, while minimizing power dissipation. internal circuit protection includes thermal shutdown with hysteresis, transient-suppression diodes, and crossover-current protection. special power-up sequencing is not required. the a3972sb is supplied in a 24-pin plastic dip with two batwing power tabs (suffix ?b?). the power tabs are at ground potential and need no electrical isolation. the device is lead (pb) free with 100% matte tin leadframe plating. 29319.33, rev. d features and benefits ? 1.5 a, 50 v continuous output rating ? low r ds(on) dmos output drivers ? optimized microstepping via 6-bit linear dacs ? programmable mixed, fast, and slow current-decay modes ? 4 mhz internal oscillator for digital timing ? serial-interface controls chip functions ? synchronous rectification for low power dissipation ? internal uvlo and thermal shutdown circuitry ? crossover-current protection ? precision 2 v reference ? inputs compatible with 3.3 or 5 v control signals ? sleep and idle modes package: 24-pin dip with 4 fused leads (suffix b) pin-out diagram not to scale a3972 dual dmos full-bridge microstepping pwm motor driver
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 2 selection guide part number packing A3972SB-T 15 pieces/tube absolute maximum ratings characteristic symbol notes rating units load supply voltage v bb 50 v output current* i out 1.5 a logic supply voltage v dd 7.0 v logic input voltage range v in ?0.3 to v dd + 0.3 v reference voltage v ref 3v sense voltage (dc) v s 500 mv package power dissipation p d 3.1 w operating ambient temperature t a range s ?20 to 85 oc junction temperature t j 150 oc storage temperature t stg ?55 to 150 oc *output current rating may be limited by duty cycle, ambient temperature, and heat sinking. under any set of conditions, do no t exceed the speci ed current rating or a junction temperature of 150c.
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 3 functional block diagram copyright ? 2000, allegro microsystems, llc control logic regulator uvlo and fault detect out 1a sense 1 gate drive charge pump v reg cp1 cp2 v cp v bb1 bandgap osc serial port clock data strobe out 1b 0.22 m f +- v dd phase 1/2 sync. rect. mode sync. rect. disable mode 1/2 0.22 m f 0.22 m f ref out 2a v bb2 out 2b sense 2 programmable pwm timer fixed-off blank mixed decay programmable pwm timer fixed-off blank mixed decay 6-bit linear dac +- sense 1 v cp 2 v 2 v ground mux oscilator osc select/ divider buffer 0.1 m f sleep dmos h-bridge dmos h-bridge 15 14 24 11 12 10 23 13 17 21 16 20 8 4 9 5 1 32 22 6 7 18 19 load supply logic supply 0.1 m f dwg. fp-050-1 6 6 6-bit linear dac
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 4 electrical characteristics at t a = +25c, v bb = 50 v, v dd = 5.0 v, v s = 0.5 v, f pwm < 50 khz (unless otherwise noted). limits characteristic symbol test conditions min. typ. max. units load supply voltage range v bb operating 15 ? 50 v during sleep mode 0 ? 50 v logic supply voltage range v dd operating 4.5 5.0 5.5 v load supply current i bb f pwm < 50 khz ? ? 8.0 ma operating, outputs disabled ? ? 6.0 ma sleep or idle mode ? ? 20 a logic supply current i dd f pwm < 50 khz ? ? 12 ma outputs off ? ? 10 ma idle mode (d0 = 1, d18 = 0) ? ? 1.5 ma sleep mode ? ? 100 a output drivers output leakage current i dss v out = v bb ? <1.0 50 a v out = 0 v ? <-1.0 -50 a output on resistance r ds(on) source driver, i out = ?1.5 a ? 0.5 0.55 ? sink driver, i out = 1.5 a ? 0.315 0.35 ? body diode forward voltage v f source diode, i f = 1.5 a ? ? 1.2 v sink diode, i f = 1.5 a ? ? 1.2 v control logic logic input voltage v in(1) 2.0 ? ? v v in(0) ? ? 0.8 v logic input current i in(1) v in = 2.0 v ? <1.0 20 a i in(0) v in = 0.8 v ? <-2.0 -20 a osc input frequency range f osc divide by one 2.5 ? 6.0 mhz (d0 =1, d13 = 0, d14 = 1) osc input duty cycle ? 40 ? 60 % input hysterisis ? v in 0.20 ? 0.40 v continued next page ...
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 5 electrical characteristics at t a = +25c, v bb = 50 v, v dd = 5.0 v, v s = 0.5 v, f pwm < 50 khz (unless otherwise noted). limits characteristics symbol test conditions min. typ. max. units control logic (continued) internal oscillator f osc osc shorted to ground 3.0 4.0 5.0 mhz r osc = 51 k ? 3.4 4.0 4.6 mhz dac accuracy (total error) e t relative to dac reference buffer ? 1/2 ? lsb output, d0 = 0, d17 = 0 reference input voltage range v ref(ext) 0.5 ? 2.6 v reference buffer offset v os ? 10 ? mv reference divider ratio v ref /v s d0 = 0, d18 = 0 ? 8.0 ? ? d0 = 0, d18 = 1 ? 4.0 ? ? reference input current i ref v ref = 2.0 v ? ? 0.5 a internal reference voltage v ref(int) 1.94 2.0 2.06 v gain (g m ) error (note 3) e g d0 = 0, d17 = 0, d18 = 0, dac = 63 ? 0 6 % d18 = 0, dac = 31 ? 0 9 % d18 = 1, dac = 63 ? 0 6 % d18 = 1, dac = 15 ? 0 10 % comparator input offset voltage v io v ref = 0 v ? 5.0 ? mv propagation delay times t pd 50% to 90%: pwm change to source on 500 800 1200 ns pwm change to source off 50 150 350 ns pwm change to sink on 500 800 1200 ns pwm change to sink off 50 150 350 ns crossover dead time t dt 300 700 900 ns thermal shutdown temperature t j ? 165 ? c thermal shutdown hysteresis ? t j ? 15 ? c uvlo enable threshold v uvlo increasing v dd 3.9 4.2 4.45 v uvlo hysteresis ? v uvlo 0.05 0.10 ? v notes: 1. typical data is for design information only. 2. negative current is de ned as coming out of (sourcing) the speci ed device terminal. 3. e g = [(v ref /range) ? v s ]/(v ref /range).
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 6 serial interface. the a3972sb is controlled via a 3-wire (clock, data, strobe) serial port. the programmable functions allow maximum exibility in con guring the pwm to the motor drive requirements. the serial data is written as two 19-bit words: 1 bit to select the word and 18 bits of data. the serial data is clocked in starting with d18. word 0 bit assignments bit function d0 word select = 0 d1 bridge 1, dac, lsb d2 bridge 1, dac, bit 2 d3 bridge 1, dac, bit 3 d4 bridge 1, dac, bit 4 d5 bridge 1, dac, bit 5 d6 bridge 1, dac, msb d7 bridge 2, dac, lsb d8 bridge 2, dac, bit 2 d9 bridge 2, dac, bit 3 d10 bridge 2, dac, bit 4 d11 bridge 2, dac, bit 5 d12 bridge 2, dac, msb d13 bridge 1 phase d14 bridge 2 phase d15 bridge 1 mode d16 bridge 2 mode d17 ref select d18 range select d1 ? d6 bridge 1 linear dac. six-bit word sets desired current level for bridge 1. setting all six bits to zero disables bridge 1, with all drivers off (see current regulation section of functional description). d7 ? d12 bridge 2 linear dac. six-bit word sets desired current level for bridge 2. setting all six bits to zero disables bridge 2, with all drivers off (see current regulation section of functional description). functional description continued next page ... d13 bridge 1 phase. this bit controls the direction of output current for load 1. d13 out 1a out 1b 0 l h 1 h l d14 bridge 2 phase. this bit controls the direction of output current for load 2. d14 out 2a out 2b 0 l h 1 h l d15 bridge 1 mode. d15 mode 0 mixed-decay 1 slow-decay d16 bridge 2 mode. d16 mode 0 mixed-decay 1 slow-decay d17 ref select. this bit determines the reference input for the 6-bit linear dacs. d17 reference voltage 0 internal 2 v 1 external (3 v max) d18 g m range select. this bit determines the scaling factor (4 or 8) used. d18 divider load current 0 1/8 i trip = v dac /8r s 1 1/4 i trip = v dac /4r s
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 7 for example, with a master oscillator frequency of 4 mhz, the xed off-time will be adjustable from 1.75 s to 63.75 s in increments of 2 s. d8 ? d11 fast decay time. these four bits set the fast- decay portion of xed off-time for the internal pwm control circuitry. the fast-decay portion is de ned by: t fd = [(1 + n) x 8/f osc ] - 1/f osc where n = 0?.15 for example, with an oscillator frequency of 4 mhz, the fast- decay time will be adjustable from 1.75 s to 31.75 s in incre- ments of 2 s. for t fd > t off , the device will effectively operate in fast-decay mode. d12 ? d13 oscillator control. a 4 mhz internal oscillator is used for the timing functions and charge-pump clock. if more precise control is required, an external oscillator can be input to the osc terminal. to accommodate a wider range of system clocks, an internal divider is provided to generate the desired mo frequency according to the following table: d13 d12 osc 0 0 4 mhz internal clock 0 1 external clock 1 0 external clock/2 1 1 external clock/4 d14 ? d15 synchronous recti cation. d15 d14 synchronous recti er 0 0 active 0 1 disabled 1 0 passive 1 1 low side only the different modes of operation are in the synchronous recti - cation section of the functional description. d16, d17. these bits are reserved for testing and should be programmed to zero during normal operation. d18 idle mode. the device can be placed in a low power ?idle? mode by writing a ?0? to d18. the outputs will be dis- abled, the charge pump will be turned off, and the device will draw a lower load supply currrent. the undervoltage monitor circuit will remain active. d18 should be programmed high for 1 ms before attempting to enable any output driver. word 1 bit assignments bit function d0 word select = 1 d1 blank-time lsb d2 blank-time msb d3 off-time lsb d4 off-time bit 1 d5 off-time bit 2 d6 off-time bit 3 d7 off-time msb d8 fast-decay time lsb d9 fast-decay time bit 1 d10 fast-decay time bit 2 d11 fast-decay time msb d12 c0 oscillator control d13 c1 oscillator control d14 sr control bit 1 d15 sr control bit 2 d16 reserved for testing d17 reserved for testing d18 idle mode d1 ? d2 blank time. these two bits set the blank time for the current-sense comparator. when a source driver turns on, a current spike occurs due to the reverse-recovery currents of the clamp diodes and/or switching transients related to distributed capacitance in the load. to prevent this current spike from er- roneously resetting the source-enable latch, the sense comparator is blanked. the blank timer runs after the off-time counter to provide the programmable blanking function. the blank timer is reset when phase is changed. d2 d1 time 0 0 4/ f osc 0 1 6/ f osc 1 0 8/ f osc 1 1 12/ f osc d3 ? d7 fixed off time. these ve bits set the xed off-time for the internal pwm control circuitry. fixed off-time is de ned by: t off = [(1 + n) x 8/f osc ] - 1/f osc where n = 0?.31 functional description (continued) continued next page ...
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 8 v reg . this internally generated supply voltage is used to run the sink-side dmos outputs. v reg is internally monitored and in the case of a fault condition, the outputs of the device are disabled. the v reg pin should be decoupled with a 0.22 f capacitor to ground. current regulation. the reference voltage can be set by ana- log input to the ref terminal, or via the internal 2 v precision reference. the choice of reference voltage and sense resistor set the maximum trip current. i tripmax = v ref /(range x r s ) microstepping current levels are set according to the following equations: i trip = v dac /(range x r s ) v dac = [(1 + dac) x v ref ]/64 where dac input code equals 1 to 63 and range is 4 or 8 as selected by word 0, d18. programming the dac input code to zero disables the bridge, and results in minimum load current. pwm timer function. the pwm timer is programmable via the serial port to provide xed off-time pwm signals to the con- trol block. in mixed-decay mode, the rst portion of the off time operates in fast decay, until the fast-decay time count is reached, followed by slow decay for the rest of the xed off-time period. if the fast-decay time is set longer than the off-time, the device effectively operates in fast-decay mode. oscillator. the pwm timer is based on an oscillator input, typically 4 mhz. the a3972sb can be con gured to select ei- ther a 4 mhz internal oscillator or, if more precision is required, an external clock can be connected to the osc terminal. if an external clock is used, three internal divider choices are select- able via the serial port to allow exibility in choosing f osc , based on available system clocks. if the internal oscillator op- tion is used, the absolute accuracy is dependent on the process variation of resistance and capacitance. a precision resistor can be connected from the osc terminal to v dd to further improve the tolerance. the frequency will be: f osc = 204 x 10 9 /r osc if the internal oscillator is used without the external resistor, the osc terminal should be connected to ground. sleep mode. the input terminal sleep is dedicated to putting the device into a minimum current draw mode. when pulled low, the serial port will be reset to all zeros and all circuits will be disabled. shutdown. in the event of a fault due to excessive junction temperature, or low voltage on v cp or v reg , the outputs of the device are disabled until the fault condition is removed. at power up, or in the event of low v dd , the uvlo circuit disables the drivers and resets the data in the serial port to zeros. synchronous recti cation. when a pwm off-cycle is triggered, either by a bridge disable command or internal xed off-time cycle, the load current will recirculate according to the decay mode selected by the control logic. the a3972sb synchronous recti cation feature will turn on the appropriate mosfet(s) during the current decay and effectively short out the body diodes with the low r ds(on) driver. this will lower power dissipation signi cantly and can eliminate the need for external schottky diodes for most applications. four distinct modes of operation can be con gured with the two serial port control bits: 1. active mode . prevents reversal of load current by turning off synchronous recti cation when a zero current level is detected. 2. passive mode. allows reversal of current but will turn off the synchronous recti er circuit if the load current inver- sion ramps up to the current limit. 3. disabled. mosfet switching will not occur during load recirculation. this setting would only be used with four external clamp diodes per bridge. 4. low side only. the low-side mosfets will switch on during the off time to short out the current path through the mosfet body diode. with this setting, the high-side mosfets will not synchronously rectify so four external diodes from output to supply are recommended. this mode is intended for use with high-power applications where it is desired to save the expense of two external diodes per bridge. in this mode, the sink-side mosfets are chopped during the pwm off time. in all other cases, the source-side mosfets are chopped in response to a pwm off com- mand. continued next page ... functional description (continued)
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 9 current sensing. to minimize inaccuracies in sensing the i peak current level caused by ground-trace ir drops, the sense resistor should have an independent ground return to the ground terminal of the device. for low-value sense resistors, the ir drops in the sense resistor?s pcb traces can be signi cant and should be taken into account. the use of sockets should be avoided as they can introduce variation in r s due to their contact resistance. thermal protection. circuitry turns off all drivers when the junction temperature reaches 165c typically. it is intended only to protect the device from failures due to excessive junction temperature and should not imply that output short circuits are permitted. thermal shutdown has a hysteresis of approximately 15c. serial port write timing operation. data is clocked into a shift register on the rising edge of clock signal. normally, strobe will be held high, and only will be brought low to initiate a write cycle. the data is written msb rst, followed by the word-select bit. refer to serial port diagram for timing requirements. applications information a. minimum data setup time .......................................15 ns b. minimum data hold time ........................................10 ns c. minimum setup strobe to clock rising edge ........150 ns d. minimum clock high pulse width ...........................40 ns e. minimum clock low pulse width ............................40 ns f. minimum setup clock rising edge to strobe ...........50 ns g . minimum strobe pulse width .................................150 ns h. minimum setup sleep to strobe falling ...................50 s layout. the printed wiring board should use a heavy ground plane. for optimum electrical and thermal performance, the driver should be soldered directly onto the board. the ground side of r s should have an individual path to the ground pin(s) of the driver. this path should be as short as physically possible and should not have any other components connected to it. the load supply pin, v bb , should be decoupled with an electrolytic capacitor (>47 f is recommended) placed as close to the driver as is possible. data clock dwg. wp-038-1 strobe a f b g c d e d18 d0 h sleep d17
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 10 2 1.185 0.250 0.430 0.210 0.300 0.010 0.018 0.100 0.130 0.060 0.005 1 24 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area all dimensions nominal, not for tooling use (reference jedec ms-001 be) dimensions in inches pins 6, 7, 18 and 19 internally fused b package, 24-pin dip
allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com dual dmos full-bridge microstepping pwm motor driver a3972 11 copyright ?2000-2013, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions a s may be required to permit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, llc assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com

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